The complexity of computer systems has increased exponentially over the last few decades. Along with this exponential increase in computer system complexity, there has been a corresponding exponential increase in the complexity of storage (i.e., memory) devices, which are typically required to facilitate the operation of these computer systems. Due to this increase in memory device complexity, it has become increasingly difficult to test the internal circuitry of memory devices. For example, in the case of random access memory (RAM), the traditional method of testing involves writing predetermined patterns of 1's and 0's into memory cells of a RAM device and then reading from these same memory cells so as to verify that the RAM device, and, in particular, the memory cells, operate in a proper manner. However, this method is inadequate for detecting faults in the complex row and column circuitry that is included in virtually all RAM devices. For example, if a short or an open circuit occurs in the row or column decode circuitry of a RAM device, only half of the memory may be addressed and the RAM device could still pass a test based on the above-described traditional method of testing by reading back the same pattern that was written into memory cells of the RAM device that were actually addressed.
One solution for overcoming the above-described inadequacies associated with the above-described traditional method of testing is to write diagonal patterns of 1's and 0's into memory cells of a RAM device so as to guarantee that every row of the RAM device is working. Additional diagonal patterns of 1's and 0's must also be written into memory cells of the RAM device so as to guarantee that every column of the RAM device is working. As can be easily understood, this testing method requires a significant memory requirement to store the diagonal test patterns and a lengthy computation time to perform the test, both of which can result in increased cost and complexity.
Another testing problem has arisen due to the increase in memory device complexity. That is, the increased complexity of memory devices has perhaps been most noted in the area of increased density, which has allowed memory devices to essentially be included, or embedded, along with other types of circuitry in integrated circuit devices. Because an embedded memory is typically not directly accessible from the external input/output (I/O) pins of an integrated circuit device, it is difficult to fully test the embedded memory.
One solution for testing an embedded memory, as well as other types of embedded circuitry, is to employ built-in-self-test (BIST) circuitry in an integrated circuit device along with the embedded memory and the other types of embedded circuitry. BIST circuitry is essentially control circuitry which, when activated, tests embedded memory and other types of embedded circuitry within an integrated circuit device. For example, in the case of an embedded RAM, BIST circuitry can test the embedded RAM using one of the above-described testing methods. However, the BIST circuitry is faced with the same inadequacies and shortcomings in these testing methods as have been described above. That is, the inadequacies associated with the above-described traditional testing method and the increased cost and complexity associated with the above-described diagonal pattern testing method will also be encountered by the BIST circuitry.
In view of the foregoing, it would be desirable to provide a technique for testing memory which overcomes the above-described inadequacies and shortcomings. More particularly, it would be desirable to provide a technique for testing a memory array and related circuitry in an efficient and cost effective manner.